TY - JOUR
T1 - A High-Efficiency Dual-Mode DC–DC Converter With a Low-Cost Seamless Transition Scheme
AU - Hao, Yun
AU - Wang, Xukun
AU - Han, Zhigang
AU - Huang, Chunli
AU - Xie, Huikai
AU - Zhou, Bo
N1 - Publisher Copyright:
© 1986-2012 IEEE.
PY - 2025
Y1 - 2025
N2 - A low-complexity pulsewidth modulation/ pulse skipping modulation (PWM/PSM) dual-mode buck dc–dc converter is proposed. The converter operates in PWM with a 1.5-MHz switching frequency in heavy load scenarios and switches to PSM with a sliding switching frequency under light load conditions, ensuring a high efficiency over a wide load range. Based on peak current mode control, only one simple voltage detector is required to regulate the converter for different loads, which significantly reduces the circuit complexity for a seamless mode transition. Fabricated in 180-nm BCD technology, the total chip area is less than 0.28 mm2 and the quiescent current is lower than 90 μA. The converter achieves the efficiencies up to 93.65% for PWM scheme and more than 80.61% in PSM mode, respectively, with the input voltage of 4.0–5.5 V and the load current up to 1.2 A. Additionally, the presented design achieves a line regulation less than 0.18% and a load regulation lower than 0.98%, and also accomplishes a voltage variation of 3.49%/A for load current transient response and gets an attractive figure of merit.
AB - A low-complexity pulsewidth modulation/ pulse skipping modulation (PWM/PSM) dual-mode buck dc–dc converter is proposed. The converter operates in PWM with a 1.5-MHz switching frequency in heavy load scenarios and switches to PSM with a sliding switching frequency under light load conditions, ensuring a high efficiency over a wide load range. Based on peak current mode control, only one simple voltage detector is required to regulate the converter for different loads, which significantly reduces the circuit complexity for a seamless mode transition. Fabricated in 180-nm BCD technology, the total chip area is less than 0.28 mm2 and the quiescent current is lower than 90 μA. The converter achieves the efficiencies up to 93.65% for PWM scheme and more than 80.61% in PSM mode, respectively, with the input voltage of 4.0–5.5 V and the load current up to 1.2 A. Additionally, the presented design achieves a line regulation less than 0.18% and a load regulation lower than 0.98%, and also accomplishes a voltage variation of 3.49%/A for load current transient response and gets an attractive figure of merit.
KW - Buck
KW - dc–dc converter
KW - high efficiency
KW - low complexity
KW - pulse skipping modulation (PSM)
KW - pulsewidth modulation (PWM)
KW - seamless mode transition
UR - http://www.scopus.com/pages/publications/86000793857
U2 - 10.1109/TPEL.2025.3547857
DO - 10.1109/TPEL.2025.3547857
M3 - Article
AN - SCOPUS:86000793857
SN - 0885-8993
VL - 40
SP - 12488
EP - 12498
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 9
ER -