TY - GEN
T1 - SMP-NoC
T2 - 24th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2024
AU - Wu, Teng
AU - He, Ying
AU - Wei, Shengjun
AU - Hu, Changzhen
N1 - Publisher Copyright:
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.
PY - 2025
Y1 - 2025
N2 - Network-on-Chip (NoC) is crucial for modern multicore systems, offering high throughput and low latency. However, its shared memory faces threats like illegal access and DDoS attacks. To enhance security, Memory Protection Units (MPUs) with permission tables are used to control access. NoC-MPU architecture uses TLBs and permission tables for request checks and domain isolation via CIDs, but this can cause high latency. To address this, DPU and NSM are combined for dynamic permission updates, though the tables remain static. Our paper introduces a novel Flexible and Efficient Real-Time Memory Protection Unit for NoC, featuring a hardware sandbox and taint-track monitor for pre-testing access requests. It supports dynamic memory region adjustments based on four permissions (RX, RWX, RW, R) and includes an access controller to counter DoS and side channel attacks. The design significantly boosts NoC security with minimal overheads: just 6.2% in throughput, 7.8% in area, and 4.8% in power, outperforming current solutions.
AB - Network-on-Chip (NoC) is crucial for modern multicore systems, offering high throughput and low latency. However, its shared memory faces threats like illegal access and DDoS attacks. To enhance security, Memory Protection Units (MPUs) with permission tables are used to control access. NoC-MPU architecture uses TLBs and permission tables for request checks and domain isolation via CIDs, but this can cause high latency. To address this, DPU and NSM are combined for dynamic permission updates, though the tables remain static. Our paper introduces a novel Flexible and Efficient Real-Time Memory Protection Unit for NoC, featuring a hardware sandbox and taint-track monitor for pre-testing access requests. It supports dynamic memory region adjustments based on four permissions (RX, RWX, RW, R) and includes an access controller to counter DoS and side channel attacks. The design significantly boosts NoC security with minimal overheads: just 6.2% in throughput, 7.8% in area, and 4.8% in power, outperforming current solutions.
KW - Network-on-Chip(NoC)
KW - hardware-level sandbox
KW - shared Memory
KW - taint-track monitor
UR - http://www.scopus.com/pages/publications/85219179052
U2 - 10.1007/978-981-96-1545-2_1
DO - 10.1007/978-981-96-1545-2_1
M3 - Conference contribution
AN - SCOPUS:85219179052
SN - 9789819615445
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 1
EP - 11
BT - Algorithms and Architectures for Parallel Processing - 24th International Conference, ICA3PP 2024, Proceedings
A2 - Zhu, Tianqing
A2 - Li, Jin
A2 - Castiglione, Aniello
PB - Springer Science and Business Media Deutschland GmbH
Y2 - 29 October 2024 through 31 October 2024
ER -