Scalable Hardware Architecture for High-Throughput Implementation of ESPRIT Algorithm

Estimating signal parameter via rotational invariance technique (ESPRIT) algorithm is a high-performance method for direction of arrival (DOA) estimation. Its most cumbersome aspect is performing eigenvalue decomposition twice, particularly with general square matrices. Current implementations lack flexibility in configuring the number of array elements, signal sources, and snapshots at the same time. To tackle these challenges, we propose a scalable hardware acceleration scheme for the QR decomposition (QRD) algorithm on a field programmable gate array (FPGA). Our QRD module leverages orientation displacement, parallel computing, and logic reuse to enhance speed and generality. Building upon this foundation, a reconfigurable design scheme with a parallel Covariance Matrix Computation (CMC) module for ESPRIT is proposed to increase calculation speed and throughput. Our ESPRIT implementation supports up to 26 array elements, 25 signal sources, and 2048 snapshots. As evidenced by experiments, the root mean squared error (RMSE) of the QRD module and ESPRIT implementation achieve 0.02 and 0.04°, respectively. On average, when the number of array elements, signal sources, and snapshots are set to 4, 1, 64 and 8, 1, 128 individually, our ESPRIT implementation completes DOA estimation in 22.04 and 60.50 μs, with throughput of 45372 and 16529 separately. In comparison with CPU implementations, our FPGA implementations offer up to 88.66% and 89.84% time savings for QRD and ESPRIT, respectively.