Complexity Reduced MLSE Equalization Assisted with Pattern-Integrated LUT for Bandwidth Efficient PAM-4 IM/DD Interconnection

The inter-symbol-interference (ISI) is the major impairment in bandwidth-efficient intensity modulation and direct detection (IM/DD) interconnection systems regarding simultaneous low power consumption and high cost-effectiveness. The ISI can be well compensated by advanced digital equalizer cooperated with maximum likelihood sequence estimation (MLSE), and look-up table (LUT) associated MLSE schemes. However, under severe ISI scenarios, the implementation complexity of the combined LUT and MLSE increases significantly as the memory length for the required LUT expands. In this paper, an MLSE scheme employing pattern-integrated LUT (PiLUT-MLSE) with a reduced stage profile is proposed and demonstrated in a bandwidth-efficient 4-level pulse amplitude modulation (PAM-4) IM/DD interconnection system. The intermediate symbols are shared in integrated patterns by simply counting the ISI between adjacent preceding and succeeding symbols to optimize the LUT size effectively. By doing so, the computational loads for subsequent MLSE path comparison and addition are significantly reduced with the assistance of the optimized PiLUT. The effectiveness of the proposed PiLUT-MLSE is validated using 112, 140, and 160 Gbit/s PAM-4 signals transmitted over distances of 2 km, 1 km, and 500 m standard single-mode fiber (SSMF), in a 3 dB bandwidth of 19 GHz. Experimental results performed in 112/140 Gbit/s PAM-4 system indicate that the PiLUT-MLSE significantly decreases the ISI impairments with 0.8/1-dB receiver power sensitivity improvement, compared with typical linear MLSE scheme at the 7% hard-decision forward error correction threshold of 3.8e-3. In addition, the proposed scheme can support the transmission of 160 Gbit/s PAM-4 signal at the bit error rate below 3.8e-3. Furthermore, the results show that even in an ultra-high bandwidth efficient system and accounting for the optimal computational complexity approach, the proposed scheme can reduce the LUT size by 75% as compared with a conventional one, thus that dynamic branch metric of MLSE equalizer can be further optimized in terms of multiplications by 100%, additions by 75% and comparator by 75%, with only a 0.1∼0.4 dB penalty in received optical power.